Simulation of Dual-Material Hetero-Double Gate Tunnel Field Effect Transistor (TFET) in Sub-Micron Region

To meet the performance requirements of low power mobile devices, a device with high ION/IOFF ratio at low-VDD is needed. TFETs are gaining popularity due to their subthreshold slope and transconductance compared MOSFETs. However, silicon-based have on-state current, which limits use in high-performance applications. overcome this limitation, using narrower band gap material like Ge can increase tunneling efficiency source side. Additionally, larger ambipolar current associated Si-TFETs be reduced by considering dual-material hetero-double-gate-dielectric (DM HDG) TFET. The main objective research propose characterize new TFET structure advantages hetero hetero-gate-dielectric TFETs, realizes an enhanced ION suppressed current. was fabricated addition hetero-dielectric Buried Oxide (BOX) on doped substrate for reduction We will adopt source-to-gate overlap technique achieve desired (SS). All simulations were done 2-D TCAD simulator Atlas Silvaco. optimized terms (ION/IOFF) other metrics simulation results available structures literature.